1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor (hereinafter referred to as TFT) of a top gate type, which is, for example, used as a switching element and the like in a liquid crystal display or organic EL (Electroluminescent) display and is formed of polysilicon on an insulating substrate.
2. Description of the Related Art
A liquid crystal display is manufactured, for example, by encapsulating liquid crystals into a clearance between a TFT substrate and a CF (Color Filter) substrate to make a liquid crystal display panel, thereafter connecting it to a TCP (Tape Carrier Package) mounted with a drive IC for driving the liquid crystal display panel and further connecting the TCP to a wiring board for supplying signals and power.
In recent years, reduction of a size and thickness has been required in a liquid crystal display of an active matrix type. To this end, several attempts have been made to configure a drive circuit by using TFTs, in addition to forming TFTs as switching elements on the TFT substrate. Polysilicon TFTs have each a semiconductor film of polysilicon with high carrier mobility and are effective to increase operation speed when they are used as thin film elements of the drive circuit. Therefore, the polysilicon TFTs are now being developed prevalently.
In the Japanese Patent No. 3185759 and the Japanese Patent Laid-Open No. 10-116989, for example, a technique is disclosed in which a first gate insulating film of silicon oxide is formed via an underlying insulating film on a polysilicon semiconductor film formed on a transparent insulating substrate, and then the semiconductor film and the first gate insulating film are etched and patterned together into island shape. Thereafter, a second gate insulating film of silicon oxide is formed on the first gate insulating film having island shape. This method effectively serves to reduce a chance of exposing the polysilicon semiconductor film to an outside air or atmosphere, protect it from contaminants, and to obtain a clean interface (between polysilicon semiconductor film and the silicon oxide film).
With this method, high carrier mobility of the polysilicon TFT and high uniformity thereof without variations can be achieved in the same substrate and between substrates.
More specifically, as shown in FIG. 1A, an underlying protection film 102 of silicon oxide (SiO2) is formed on a transparent insulating substrate 101 made of glass, and an amorphous silicon (a-Si) semiconductor film is formed on the underlying protection film 102. Next, excimer laser light is irradiated and scanned onto the semiconductor film to reform it polycrystalline. Thus, a polysilicon (p-Si) semiconductor film 103 is formed, on which a first gate oxide film 104 of silicon oxide is also formed.
Next, by using photolithography technique, the polysilicon semiconductor film 103 and the first gate oxide film 104 are etched and pattered together into an island shape so as to form an island part 105 as shown in FIG. 1B.
When the island part 105 is formed by etching, selectivity of polysilicon and silicon oxide (defined by an etching speed of polysilicon/an etching speed of silicon oxide) is set to a comparatively high value.
The reason why the high value is set as the selectivity is because, when the selectivity is comparatively low, the silicon oxide of the underlying protection film 102 is etched excessively and, as a result, the island part 105 has a wide step due to an undercut part 106 shown in FIG. 2. Such a step results in disconnection of electrodes formed in the subsequent process or deterioration of yield due to a leak current flowing between the electrodes and the semiconductor film 103. Furthermore, an undulation part 107 is formed on the surface of the underlying protection film 102 and lowers light transmittance of the transparent insulating substrate 101. This brings about degradation of the quality of liquid crystal displays when such an undulated transparent insulating substrate 101 is used.
After the above processing, as shown in FIG. 1C, a second gate oxide film 108 of silicon oxide is formed on the transparent insulating substrate 101 with the semiconductor film 103 and the first gate oxide film 104. Next, a conductive film composed of tantalum and the like is formed above the second gate oxide film 108 by spattering and the like, and is then patterned using photolithography technique to form a gate electrode 109 on the second gate oxide film 108, as shown in FIG. 1D.
Next, by using the gate electrode 109 as a mask, an impurity ion such as a phosphorus ion is implanted into the polysilicon semiconductor film 103 to form source/drain areas. Then, an interlayer insulating film 110 of silicon oxide is formed, as shown in FIG. 1D.
Next, as shown in FIG. 1E, contact holes are formed and thereafter, source/drain electrodes 111 are formed to be connected to the source/drain areas.
In the conventional technique described above, however, the comparatively high selectivity of the polysilicon and silicon oxide in dry etching to form the island part 105 results in the formation of an overhang part 105a shown in FIG. 1B. At the overhang part 105a, an end portion or part of the first gate oxide film 104 projects outwardly from an end surface of the semiconductor film 103. Under the circumstances, when the second gate oxide film 108 is formed in this status, coverage becomes insufficient on the side walls of the island part 105, as shown in FIG. 1C.
This phenomenon occurs also when the interlayer insulating film 110 and the source/drain electrodes 111 are formed, as shown in FIGS. 1D and 1E. Therefore, there is a disadvantage that disconnection or connection failures of electrodes unfavorably take place and thus the yield is deteriorated because of defective transistors.
To overcome the disadvantage, the Japanese Patent Laid-Open No. 2001-332741 proposes another technique in which, after the semiconductor film 103 and the first gate oxide film 104 are etched together into island shape, the first gate oxide film 104 is removed, and then the second gate oxide film 108 is formed. However, there still exists a disadvantage that contamination is not avoidable on the surface of the semiconductor film 103 because the semiconductor film 103 is not covered until the second gate oxide film 108 is formed.